Integrated circuit memory includes dynamic random access memory (DRAM) and static random access memory (SRAM). DRAM cells provide good memory density, but are relatively slow. SRAM cells are faster than DRAM cells, but the required area for SRAM cells is large. The large area associated with six-transistor and four-transistor memory cells has limited the design of high density static random access memory (SRAM) devices.
Negative Differential Resistance (NDR) devices have been used to reduce the number of elements per memory cell. However, NDR devices tend to suffer from problems such as high standby power consumption, high operating voltages, low speeds and complicated fabrication processes.
F. Nemati and J. D. Plummer have disclosed a two-device thyristor-based SRAM cell (TRAM) that includes an access transistor and a gate-assisted, vertical thyristor. The disclosed vertical p+/n/p/n+ thyristor is operated in a gate-enhanced switching mode to provide the memory cell with SRAM-like performance and DRAM-like density. The performance of the TRAM cell depends on the turn-off characteristics of the vertical thyristor, and the turn-off characteristics depend on the stored charge and carrier transit time in the p-region of the p+/n/p/n+ thyristor. The turn-off characteristics for the vertical thyristor is improved from milliseconds to five nanoseconds by reverse biasing the thyristor for a write-zero operation and by using a gate to assist with turn-off switching of the thyristor by discharging the stored charge. Even so, the geometry and vertical height of the vertical thyristor's p-region limits the turn-off characteristics and the associated cell performance of the gate-assisted, vertical thyristor disclosed by Nemati and Plummer. The scalability of the TRAM cell and the ability to control the performance of the TRAM cell are also limited.
There is a need in the art to provide improved memory cells that provide DRAM-like density, faster SRAM-like performance, and scalability.